OpenAI and Broadcom unveil LLM-optimized inference chip
Key Points
- Jalapeño: LLM inference accelerator
- Nine-month design-to-tape-out
- Early tests show higher performance-per-watt
Summary
OpenAI and Broadcom announced Jalapeño, a purpose-built inference accelerator designed from the ground up for LLM inference. Engineering samples are running production-target workloads (including GPT-5.3-Codex-Spark) at target frequency and power; early lab tests report substantially better performance-per-watt than current state-of-the-art. The chip and surrounding platform were co-developed in nine months using OpenAI models to accelerate design and optimization, and will be deployed in a multi-generation rack and networking platform (Broadcom silicon, Tomahawk networking, Celestica integration) targeted for gigawatt-scale datacenters beginning in 2026. A detailed technical performance report is forthcoming.
Key Points
- Purpose-built for inference: blank-slate architecture optimized for LLM kernels, memory movement, networking, and low-latency serving (not a repurposed general-purpose accelerator).
- Early lab results: engineering samples run at production target frequency/power; early testing indicates significantly better performance-per-watt versus current accelerators (detailed benchmarks to follow).
- System co-design: architecture reduces data movement and balances compute, memory, and networking to increase realized utilization closer to theoretical peak.
- Rapid ASIC cycle: design-to-tape-out completed in nine months, enabled by software–hardware co-development and use of OpenAI models to accelerate optimizations.
- Production path: Broadcom provides silicon and Tomahawk networking; Celestica handles board/rack/system integration; platform is planned for multi-generation deployment at gigawatt scale with partners.
- Practical implications for engineers:
- Expect to adapt inference stacks (kernels, memory tiling, scheduling, network-aware partitioning) to exploit the architecture.
- Plan to benchmark real workloads once the technical report and sample/board-level data are published.
- Anticipate vendor integration at rack/network level (Tomahawk networking, Broadcom boards, Celestica systems) rather than a standalone GPU drop-in.
Next actions
- Track the forthcoming technical report for power, latency, and throughput benchmarks.
- Start inventorying inference-kernel dependencies and network-aware sharding strategies to prepare for porting/optimization.
- Engage vendor channels for early-access samples, board specs, and integration guidance when available.